Standard-compliant Decimal Floating Point Adder / Subtractor
Mon, 04/10/2010 - 15:06 | 
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Thesis Title:
Standard-compliant Decimal Floating Point Adder / Subtractor
Name:
Ghada Mohamed Awad El-Gendy
Date of Birth:
Fri, 08/12/1967
Nationality:
Egyptian
E-mail:
Degree:
Master
Previous Degrees:
B.Sc. (ELC) 1990 – Cairo
Registration Date:
Tue, 01/10/2002
Awarding Date:
Tue, 15/12/2009
Supervisors:
Examiners:
Dr. Wahdan, A. A.
Dr. Qamar, I. M.
Dr. Habib, S. E.
Key Words:
Floating points, Subtractors, Decimal numbers, Rounding testing
Summary:
The design performs addition and subtraction on 64-bit operands in a single path
adder with exception and rounding handling fulfilling the final version of the
IEEE Standard for Floating-Point Arithmetic P754 which was published in
August 2008. We introduced two different implementations for the BCD-adder,
BCD-subtractor internal design as well as different architecture. Complete test
and verification is performed on all the design versions fulfilling 3063 test vectors
supplied by IBM Corp. and supporting 2 extra rounding modes proposed by
IBM.
